// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
// Date        : Sat Dec  4 22:27:05 2021
// Host        : LAPTOP-HCDIGOGC running 64-bit major release  (build 9200)
// Command     : write_verilog -mode timesim -nolib -sdf_anno true -force -file
//               D:/vivadofiles/test1011/test1011.sim/sim_1/impl/timing/xsim/eb_1011test_sim_time_impl.v
// Design      : eb_1011test
// Purpose     : This verilog netlist is a timing simulation representation of the design and should not be modified or
//               synthesized. Please ensure that this netlist is used with the corresponding SDF file.
// Device      : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
`define XIL_TIMING

module bzc
   (data_out_OBUF,
    clk_IBUF_BUFG,
    data_out_reg_0,
    data_in_IBUF,
    en_IBUF,
    E,
    lopt);
  output data_out_OBUF;
  input clk_IBUF_BUFG;
  input data_out_reg_0;
  input [7:0]data_in_IBUF;
  input en_IBUF;
  input [0:0]E;
  output lopt;

  wire [0:0]E;
  wire clk_IBUF_BUFG;
  wire [7:0]data_in_IBUF;
  wire data_out_OBUF;
  wire data_out_i_1_n_0;
  wire data_out_reg_0;
  wire data_out_reg_lopt_replica_1;
  wire [6:6]data_temp;
  wire \data_temp_reg_n_0_[0] ;
  wire \data_temp_reg_n_0_[1] ;
  wire \data_temp_reg_n_0_[2] ;
  wire \data_temp_reg_n_0_[3] ;
  wire \data_temp_reg_n_0_[4] ;
  wire \data_temp_reg_n_0_[5] ;
  wire en_IBUF;
  wire [6:0]p_0_in;

  assign lopt = data_out_reg_lopt_replica_1;
  LUT3 #(
    .INIT(8'hB8)) 
    data_out_i_1
       (.I0(data_in_IBUF[7]),
        .I1(en_IBUF),
        .I2(data_temp),
        .O(data_out_i_1_n_0));
  FDCE #(
    .INIT(1'b0)) 
    data_out_reg
       (.C(clk_IBUF_BUFG),
        .CE(1'b1),
        .CLR(data_out_reg_0),
        .D(data_out_i_1_n_0),
        .Q(data_out_OBUF));
  (* OPT_INSERTED_REPDRIVER *) 
  (* OPT_MODIFIED = "SWEEP " *) 
  FDCE #(
    .INIT(1'b0)) 
    data_out_reg_lopt_replica
       (.C(clk_IBUF_BUFG),
        .CE(1'b1),
        .CLR(data_out_reg_0),
        .D(data_out_i_1_n_0),
        .Q(data_out_reg_lopt_replica_1));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \data_temp[0]_i_1 
       (.I0(en_IBUF),
        .I1(data_in_IBUF[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_temp[1]_i_1 
       (.I0(data_in_IBUF[1]),
        .I1(en_IBUF),
        .I2(\data_temp_reg_n_0_[0] ),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_temp[2]_i_1 
       (.I0(data_in_IBUF[2]),
        .I1(en_IBUF),
        .I2(\data_temp_reg_n_0_[1] ),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_temp[3]_i_1 
       (.I0(data_in_IBUF[3]),
        .I1(en_IBUF),
        .I2(\data_temp_reg_n_0_[2] ),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_temp[4]_i_1 
       (.I0(data_in_IBUF[4]),
        .I1(en_IBUF),
        .I2(\data_temp_reg_n_0_[3] ),
        .O(p_0_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_temp[5]_i_1 
       (.I0(data_in_IBUF[5]),
        .I1(en_IBUF),
        .I2(\data_temp_reg_n_0_[4] ),
        .O(p_0_in[5]));
  LUT3 #(
    .INIT(8'hB8)) 
    \data_temp[6]_i_1 
       (.I0(data_in_IBUF[6]),
        .I1(en_IBUF),
        .I2(\data_temp_reg_n_0_[5] ),
        .O(p_0_in[6]));
  FDRE #(
    .INIT(1'b0)) 
    \data_temp_reg[0] 
       (.C(clk_IBUF_BUFG),
        .CE(E),
        .D(p_0_in[0]),
        .Q(\data_temp_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \data_temp_reg[1] 
       (.C(clk_IBUF_BUFG),
        .CE(E),
        .D(p_0_in[1]),
        .Q(\data_temp_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \data_temp_reg[2] 
       (.C(clk_IBUF_BUFG),
        .CE(E),
        .D(p_0_in[2]),
        .Q(\data_temp_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \data_temp_reg[3] 
       (.C(clk_IBUF_BUFG),
        .CE(E),
        .D(p_0_in[3]),
        .Q(\data_temp_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \data_temp_reg[4] 
       (.C(clk_IBUF_BUFG),
        .CE(E),
        .D(p_0_in[4]),
        .Q(\data_temp_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \data_temp_reg[5] 
       (.C(clk_IBUF_BUFG),
        .CE(E),
        .D(p_0_in[5]),
        .Q(\data_temp_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \data_temp_reg[6] 
       (.C(clk_IBUF_BUFG),
        .CE(E),
        .D(p_0_in[6]),
        .Q(data_temp),
        .R(1'b0));
endmodule

(* ECO_CHECKSUM = "56b153f6" *) 
(* NotValidForBitStream *)
module eb_1011test
   (rst,
    clk,
    en,
    data_in,
    out,
    data_out);
  input rst;
  input clk;
  input en;
  input [7:0]data_in;
  output out;
  output data_out;

  wire clk;
  wire clk_IBUF;
  wire clk_IBUF_BUFG;
  wire [7:0]data_in;
  wire [7:0]data_in_IBUF;
  wire data_out;
  wire data_out_OBUF;
  wire en;
  wire en_IBUF;
  wire lopt;
  wire out;
  wire out0;
  wire out00_out;
  wire out_OBUF;
  wire rst;
  wire rst_IBUF;
  wire t1011_n_0;

initial begin
 $sdf_annotate("eb_1011test_sim_time_impl.sdf",,,,"tool_control");
end
  bzc btc
       (.E(rst_IBUF),
        .clk_IBUF_BUFG(clk_IBUF_BUFG),
        .data_in_IBUF(data_in_IBUF),
        .data_out_OBUF(data_out_OBUF),
        .data_out_reg_0(t1011_n_0),
        .en_IBUF(en_IBUF),
        .lopt(lopt));
  BUFG clk_IBUF_BUFG_inst
       (.I(clk_IBUF),
        .O(clk_IBUF_BUFG));
  IBUF clk_IBUF_inst
       (.I(clk),
        .O(clk_IBUF));
  IBUF \data_in_IBUF[0]_inst 
       (.I(data_in[0]),
        .O(data_in_IBUF[0]));
  IBUF \data_in_IBUF[1]_inst 
       (.I(data_in[1]),
        .O(data_in_IBUF[1]));
  IBUF \data_in_IBUF[2]_inst 
       (.I(data_in[2]),
        .O(data_in_IBUF[2]));
  IBUF \data_in_IBUF[3]_inst 
       (.I(data_in[3]),
        .O(data_in_IBUF[3]));
  IBUF \data_in_IBUF[4]_inst 
       (.I(data_in[4]),
        .O(data_in_IBUF[4]));
  IBUF \data_in_IBUF[5]_inst 
       (.I(data_in[5]),
        .O(data_in_IBUF[5]));
  IBUF \data_in_IBUF[6]_inst 
       (.I(data_in[6]),
        .O(data_in_IBUF[6]));
  IBUF \data_in_IBUF[7]_inst 
       (.I(data_in[7]),
        .O(data_in_IBUF[7]));
  (* OPT_MODIFIED = "SWEEP " *) 
  OBUF data_out_OBUF_inst
       (.I(lopt),
        .O(data_out));
  IBUF en_IBUF_inst
       (.I(en),
        .O(en_IBUF));
  OBUF out_OBUF_inst
       (.I(out_OBUF),
        .O(out));
  LUT2 #(
    .INIT(4'hB)) 
    out_i_2
       (.I0(en_IBUF),
        .I1(rst_IBUF),
        .O(out0));
  FDCE #(
    .INIT(1'b0)) 
    out_reg
       (.C(clk_IBUF_BUFG),
        .CE(1'b1),
        .CLR(out0),
        .D(out00_out),
        .Q(out_OBUF));
  IBUF rst_IBUF_inst
       (.I(rst),
        .O(rst_IBUF));
  test1011 t1011
       (.CLK(clk_IBUF_BUFG),
        .E(rst_IBUF),
        .data_out_OBUF(data_out_OBUF),
        .out00_out(out00_out),
        .out_OBUF(out_OBUF),
        .rst(t1011_n_0));
endmodule

module test1011
   (rst,
    out00_out,
    CLK,
    out_OBUF,
    E,
    data_out_OBUF);
  output rst;
  output out00_out;
  input CLK;
  input out_OBUF;
  input [0:0]E;
  input data_out_OBUF;

  wire \/i__n_0 ;
  wire CLK;
  wire [0:0]E;
  wire data_out_OBUF;
  wire out00_out;
  wire out_OBUF;
  wire out_i_1_n_0;
  wire res;
  wire rst;
  wire [1:0]state;

  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'h4A)) 
    \/i_ 
       (.I0(state[0]),
        .I1(state[1]),
        .I2(data_out_OBUF),
        .O(\/i__n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \FSM_sequential_state[1]_i_1 
       (.I0(E),
        .O(rst));
  (* FSM_ENCODED_STATES = "s0:00,s3:11,s2:10,s1:01" *) 
  FDCE #(
    .INIT(1'b0)) 
    \FSM_sequential_state_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .CLR(rst),
        .D(data_out_OBUF),
        .Q(state[0]));
  (* FSM_ENCODED_STATES = "s0:00,s3:11,s2:10,s1:01" *) 
  FDCE #(
    .INIT(1'b0)) 
    \FSM_sequential_state_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .CLR(rst),
        .D(\/i__n_0 ),
        .Q(state[1]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'h80)) 
    out_i_1
       (.I0(data_out_OBUF),
        .I1(state[1]),
        .I2(state[0]),
        .O(out_i_1_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    out_i_1__0
       (.I0(out_OBUF),
        .I1(res),
        .O(out00_out));
  FDCE #(
    .INIT(1'b0)) 
    out_reg
       (.C(CLK),
        .CE(1'b1),
        .CLR(rst),
        .D(out_i_1_n_0),
        .Q(res));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif
